MIPS releases RISC-V CPU for autonomous vehicles

MIPS released its P8700 CPU based on the RISC-V computing architecture to target driver assistance and autonomous vehicle applications.

The San Jose, California-based company, which focuses on developing efficient and configurable intellectual property compute, licenses its designs to other chip makers. Today, it is announcing the general availability launch of the MIPS P8700 Series RISC-V Processor.

Designed to meet the low-latency, highly intensive data movement demands of the most advanced automotive applications such as ADAS (advanced driver assistance system) and autonomous vehicles, the P8700 delivers accelerated compute, power efficiency and scalability, said Sameer Wasson, CEO of MIPS, in an interview with VentureBeat.

“Automotive is a big segment where we focus. It continues being a very exciting place. Some companies came and some disappeared,” Wasson said. “They lost interest. They came out of COVID and refilled their inventory. But what’s happening in the industry right now is very interesting. I think autonomy is now coming back to that steady growth rate.”

He added, “It is one of the biggest driving forces to continue innovating in terms of bringing better solutions. If you think about the solutions today, most of the deployments in vehicles are driven by what used to be vehicle technology. That was basic microcontrollers, simple stuff. They could open and close doors, run internal combustion engines. As autonomy grows, you’re going to see compute needs evolve toward more AI network compute. That allows you to have higher levels of autonomy.”

“We have technology and we have a play in making it much more mainstream than it has been,” he said.

Typical solutions for ADAS and autonomous driving rely on a brute-force approach of embedding a higher number of cores at higher clock rates driving synthetic, albeit unrealistic and unrealized performance.

The P8700 with its multi-threaded and power-efficient architecture allows MIPS customers to implement fewer CPU cores and much lower thermal design power (TDP) than the current market solutions, thereby allowing OEMs to develop ADAS solutions in an affordable and highly scalable manner. It also mitigates the system bottlenecks of data movement inefficiency by providing highly efficient, optimized and lower power latency sensitive solution specifically tailored for interrupt laden multi-sensor platforms.

“If you look at the RISC-V space overall, I think these spaces are ready for disruption, with a chance for new architectures coming in,” Wasson said. “Otherwise, EVs will be much more expensive than they need to be.”

For Level 2 or higher ADAS systems with AI Autonomous software stack, the MIPS P8700 can also offload core processing elements that cannot be easily quantized in deep learning and reduced by sparsity-based convolution processing functions, resulting in a greater than 30% better AI Stack software utilization and efficiency.

“The automotive market demands CPUs which can process a large amount of data from multiple sensors in real-time and feed the AI Accelerators to process in an efficient manner,” said Wasson. “The MIPS Multi-threading and other architectural hooks tailored for automotive applications, make it a compelling core for data intensive processing tasks. This will enable automotive OEMs to have high performance compute systems which consume less power and better utilize of AI Accelerators.”

The MIPS P8700 core, featuring multi-core/multi-cluster and multi-threaded CPU IP based on the RISC-V ISA, is now progressing toward series production with multiple major OEMs. Key customers like Mobileye (Nasdaq: MBLY) have embraced this approach for future products for self-driving vehicles and highly automated driving systems.

“MIPS has been a key collaborator in our success with the EyeQ™ systems-on-chip for ADAS and autonomous vehicles,” said Elchanan Rushinek, executive vice president of engineering for Mobileye, in a statement. “The launch of the MIPS P8700 RISC-V core will help drive our continued development for global automakers, enabling greater performance and excellent efficiency in cost and power usage.” 

The P8700 Series is a high-performance out-of-order processor that implements the RISC-V RV64GC architecture, including new CPU and system-level features designed for performance, power, area form factors and additional proven features built on legacy MIPS micro-architecture deployed in more than 30+ car models today across the global OEM market.

Engineered to deliver industry-leading compute density, MIPS’ latest processor harnesses three key architectural features, including MIPS out-of-order multi-threading, which enables execution of multiple
instructions from multiple threads (harts) every clock cycle, providing higher utilization and CPU efficiency.

It also has coherent multi-core, multi-cluster, where the P8700 Series scales up to 6 coherent P8700 cores in a cluster with each cluster supporting direct attach accelerators.

And it has functional safety designed to meet the ASIL-B(D) functional safety standard (ISO26262) by incorporating several fault detection capabilities such as end-to-end parity protection on address and data buses, parity protection on software visible registers, fault bus for reporting faults to the system, and
more.

The MIPS P8700 processor is now available to the broader market, with key partnerships already in place. Shipments with OEM launches are expected shortly. MIPS has been around for three decades and billions of its chips have shipped to date.

In the past, Wasson said vendors were using the wrong computer architecture, which was built for entertainment and screen applications, rather than hardcore AI problems.

“What we are trying to do is go focus on building compute for ADAS and higher levels of autonomy, from the ground up,” he said.

Vasanth Waran, worldwide head of business development at MIPS, said in an interview with VentureBeat that other architectures have been pushing performance forward through brute force, adding more complexity and scaling, but not necessarily coming up with affordable designs.

“If you want to bring it to a larger market, you want autonomy to be affordable, and you want it to scale,” Waran said. “There needs to be a more pure approach, given the lack of a better word, and that’s what motivated us. The 8700 from the ground up is where you can move data seamlessly between different parts of a design. If you look at a car, you have a lot of sensors with data coming in, from cameras, radar, LiDAR, in some cases, and the inputs from these need to be processed. It needs to be pushed out to an AI accelerator system. And then that data needs to help you make a decision.”

MIPS’ designs try to offload a lot of the performance from AI accelerators, whether it’s in pre-processing or post-processing. With a general-purpose processor, new software can be supported, and such software for AI accelerators is changing all the time.

RISC-V has been building up its ecosystem in the past couple of years, and its ecosystem is now at the right size to support applications.

“The other big thing that’s happening is software defined vehicles. Our products can be used for a holistic software-defined vehicle architecture,” Waran said. “We’re focused completely on the autonomous journey.”

Wasson said his company will be at the CES 2025 event coming up in Las Vegas in January, where pitching automakers will be a big task for the company.